A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories1

This paper introduces the architecture and initial algorithms for Pixel-planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles/second) and for supporting algorithm and application research in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280x1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128x128-pixel array of processors-with-memory with parallel quadratic expression evaluation. Implemented on fast custom CMOS chips, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reassigned to any part of the screen or to non-screen-oriented computation. A message-passing operating system encourages algorithms to mix and match capabilities of the massively parallel rendering units with those of the math-oriented processors. As of January 1989, both hardware and software are still under construction, with initial system operation scheduled for summer 1989.